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    1,569 verilog hdl java zakázek nalezeno, ceny v EUR

    more details will be given in the chat only serious expert and my maximum budget for this task is $100

    €49 (Avg Bid)
    €49 Průměr. nabídka
    24 nabídky

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €912 (Avg Bid)
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    4 nabídky

    hello, everyone i would like to hire fpga and verilog experts if you have experience on fpga, please bid on my project. thanks.

    €466 (Avg Bid)
    €466 Průměr. nabídka
    20 nabídky

    The task is to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with [pro zobrazení URL se přihlaste]; a. The source can

    €550 (Avg Bid)
    €550 Průměr. nabídka
    3 nabídky
    find fpga projects Ukončeno left

    Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project

    €406 (Avg Bid)
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    10 nabídky
    Matlab Codnig Ukončeno left

    I need the matlab developer and verilog developer

    €550 (Avg Bid)
    €550 Průměr. nabídka
    17 nabídky

    hi, everyone i would like to hire fpga and verilog expert if you have experience on fpga, please bid. thanks.

    €457 (Avg Bid)
    €457 Průměr. nabídka
    24 nabídky

    Need to integrate HDL buspro with the HDL-ON app or iLife app

    €44 (Avg Bid)
    €44 Průměr. nabídka
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    I need someone with reporting and integrations background. Someone who is comfortable with BI Publisher, HCM Extracts and HDL.

    €501 (Avg Bid)
    €501 Průměr. nabídka
    8 nabídky
    16-point FFT Ukončeno left

    verilog code for radix-4 16 point fft

    €13 (Avg Bid)
    €13 Průměr. nabídka
    8 nabídky

    i want a verilog coding regarding radix-4 16 point FFT. so i need expert help.

    €14 (Avg Bid)
    €14 Průměr. nabídka
    4 nabídky

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €10428 (Avg Bid)
    €10428 Průměr. nabídka
    2 nabídky

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €9136 (Avg Bid)
    €9136 Průměr. nabídka
    1 nabídky

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €786 - €793
    €786 - €793
    0 nabídky

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €776 - €776
    €776 - €776
    0 nabídky

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €778 - €778
    €778 - €778
    0 nabídky

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €788 (Avg Bid)
    €788 Průměr. nabídka
    3 nabídky

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €647 - €776
    €647 - €776
    0 nabídky
    reviewing a code Ukončeno left

    hi all how are you? this is a verilog question whats output base on testbench? the codes are in txt file

    €46 (Avg Bid)
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    CS 223 Digital Design: Smart Evacuation Elevator (System Verilog) Ödevin 21 Aralık 2018'e yetişmesi gerekiyor. Ödev hakkında bilgi için lütfen iletişime geçiniz.

    €132 (Avg Bid)
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    Need to implement 16 point FFT in Verilog (Xillinx) , and use memory based LUT optimization , using the research paper attached to optimize the 16 point FFT, and compare the Area and Timing of both the optimized and un-optimized implementation. Will need a small write-up comparing both the results , complete source code of both the implementations.

    €137 (Avg Bid)
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    ...hydrogen-rich water showed a substantial increase in their antioxidant enzymes and a massive decrease in acid in the urine. Further, participants showed a significant increase in HDL the "good cholesterol," and a significant decrease in the "bad cholesterol." 'Electrolysed Reduced Water' (aka Kangen Water® or hydrogen water) has been used in hospitals in

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    Verilog Expert Ukončeno left

    I need urgent work requires Verilog expertise. It also includes a short report. More details on chat.

    €53 (Avg Bid)
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    I need to design a 4 bit adder in verilog. I will provide more details in the chat.

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    Objective is to develop one VLSI Architecture and Verilog code for Algorithm-1(2D-SRNCP) [1] with Derivative variance correlation map for given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results

    €123 (Avg Bid)
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    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

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    Verilog simulation of two action-reaction processes

    €26 (Avg Bid)
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    6 nabídky

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €157 (Avg Bid)
    €157 Průměr. nabídka
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    Need help program FPGA with Artix-7 using Verliog.

    €110 (Avg Bid)
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    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

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    Implement the Zen Protocol in the FPGA and update the Mining App

    €1073 (Avg Bid)
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    questions on Hardware Design Language and Programmable Logic Regarding Verilog or System Verilog questions. - Writing a function / typdef struct /identifing the types of errors, ... - (pulse width modulation, frequency dividers, counters, sorting, generating a sequence like a Fibonacci sequence, finite state machine, test benches, math functions

    €22 (Avg Bid)
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    Make a serial interface system using Verilog

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    ...model (just add memory and switch between memory in each cycle and do DFT). * Implement the minimum resource filter bank in VHDL in the simplest possible way. It can be done on HDL designer or Simulink VIVADO Signal Generator. * Create a word file with short explanations how VHDL model works and add guidelines what algorithm was used to implement DFT. *

    €208 (Avg Bid)
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    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width

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    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width

    €129 (Avg Bid)
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    fpga pattern generator connected to a pc starting from an evaluation board and an HDL from TI.

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    Design of a signal generator using verilog hdl. Should be done using Vivado Design Suite . More details in chat.

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    image water marking Ukončeno left

    image watermarking baed on dct algorithm in verilog code, need to implement in xilinx board

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    Part 1: Dynamic Patterns Using LEDs Requirement In this part, you are required to write a Verilog code that produces at least four different dynamic patterns, that is changing with time with reasonable speed. And those patterns are controlled by switches. Features • Use the most left switches to change the patterns. • Design your own patterns. • Use

    €121 (Avg Bid)
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    Verilog game Ukončeno left

    I have a verilog game. I need a freelancer to change the resolution of the game and add a background.

    €55 (Avg Bid)
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    Hello, I have developed the full game in verilog, but I need help with a game over screen to pop up with the player loses all of his lives or a win screen with the player has beaten the game. I will provide you with all the code, mifs, rams, and I just need help to implement the win and game over screens.

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    I want to implement the Ethernet connection. The deliverables are as follows -Verilog code to run on a Spartan 6 Board - (xc6slx100) -simulation time diagrams (more details will be given to the winner) - The code should be able to transmit and receive data at 1000mbs.

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    Simple project, that basically should detail the observed waveforms and max frequency of given code.

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    Hi Behailu D., I noticed your profile and would like to offer you my project. We can discuss any details over chat. conversion python to verilog

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    El objetivo general del presente proyecto consiste en la realización, verificación funcional y validación experimental de un microcontrolador sencillo basado en un subconjunto de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su...

    €200 (Avg Bid)
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    El objetivo general del presente proyecto consiste en la realización, verificación funcional y validación experimental de un microcontrolador sencillo basado en un subconjunto de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su...

    €213 (Avg Bid)
    €213 Průměr. nabídka
    4 nabídky