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Projekt/Soutěž Popis Nabídky/Návrhy Dovednosti Zahájeno Končí Cena EUR
Serializer & Desrializer Implementation using ZC706 and MTX___ Serializer & Desrializer Implementation using ZC706 and MTX 2 Verilog / VHDL, FPGA Apr 24, 2018 Apr 24, 20185d 23h €307
Modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think the modification won't be a big task, because the imaging processing algorithm works well, the need of modification is in controling two servos, especilly in getting back servos' position. The original demo get servos' position by using fou... 5 Verilog / VHDL, Microcontroller, Elektrotechnika, Vestavěný software, FPGA Apr 23, 2018 Apr 23, 20185d 21h €155
FPGA Design and Asic Hi there Please check the document 10 Inženýrství, Elektronika, Verilog / VHDL, Elektrotechnika, FPGA Apr 21, 2018 Apr 21, 20183d 12h €28
FPGA Design Hi there Please check the document! 6 Inženýrství, Elektronika, Verilog / VHDL, Elektrotechnika, FPGA Apr 21, 2018 Apr 21, 20183d 12h €12428
Floating Point on DSP48E1 I need to implement floating point single precision algorithm (add,sub,mul,div)(standar IEEE754) on unit DSP48E1. I need a File Register on 48bit, a priority encoder on 32b, an exponent unit where is stock the sign and exponent and a sequencer(Delay Mealy automata) who give the comand to DSP. Can anybody help me? Thank you! 6 Verilog / VHDL, FPGA Apr 21, 2018 Apr 21, 20183d 7h €193
Open source SDR and more I would like to offer my sponsorship of a software defined radio board to student engineer or researcher to work on any open source project that will involve the community. My hardware will be the BeagleSDR add-on board as best current cape for the Beagleboard-x15. It has a FPGA, AVR microcontroller, and high speed ADC/DAC, i2c programmable clock... This open source project probably last at least ... 0 Programování v C, Vestavěný software, FPGA, Linux, Softwarová architektura Apr 20, 2018 Apr 20, 201825d 16h €82
MIPS Computer Design by Verilog HDL I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL 17 Inženýrství, Verilog / VHDL, Shromažďování, Digital Design, FPGA Apr 20, 2018 Apr 20, 20182d 11h €109
Implementing Bit stuffing in verilog Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's 10 Inženýrství, Verilog / VHDL, Microcontroller, Elektrotechnika, FPGA Apr 20, 2018 Apr 20, 20181d 23h €25
Create a DLX Data Path Using VHDL Looking for an experienced person that understands computer architecture and VHDL language to complete this task. The project will require you to create simulation files of each task that's asked in the attached document to verify it works properly. The code needs to be neat and commented in a way that explains what is happening in the code. 8 Verilog / VHDL, Microcontroller, Softwarová architektura, Shromažďování, FPGA Apr 18, 2018 Apr 18, 201818h 46m €146
Do VHDL project on the ModelSim I want to do a VHDL project on ModelSim, all what you need will be in the attached document, i will need a report for the whole project ( explaining every file in the project and what it does ). I want phase 1 ( Design ) ASAP and the rest of the project within a week ( Maximum 10 days ). Please read the document carefully and if you have any questions contact me. Specify your price and time requir... 11 Inženýrství, Elektronika, Verilog / VHDL, Elektrotechnika, FPGA Apr 18, 2018 Apr 18, 20187h 32m €125
SoundLocator Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position 14 Java, Elektronika, Android, Verilog / VHDL, FPGA Apr 18, 2018 Apr 18, 20184h 23m €507
OpenCL FPGA Code modification I am looking for someone to modify the OpenCL code base of an AMD focused Crypto Mining Software and optimize it for OpenCL Based FPGA using this package [url odstraněn, pro zobrazení se přihlaste] Please respond directly with any questions such as specific mining software and such. 6 Programování v C, Verilog / VHDL, Kryptografie, OpenCL, FPGA Apr 17, 2018 Apr 17, 2018Ukončeno €1842
expert in vivado vhdl needed expert in vivado and vhdl needed asap 8 Inženýrství, Verilog / VHDL, Microcontroller, Elektrotechnika, FPGA Apr 17, 2018 Apr 17, 2018Ukončeno €21
Logisim Digital Logic Design using four bit ALU, given two numbers A and B we need to find if A is divisible by B 15 Inženýrství, Elektronika, Verilog / VHDL, Elektrotechnika, FPGA Apr 17, 2018 Apr 17, 2018Ukončeno €64
Neural Network on an FPGA I want to get a simple 3 layer (Input-Hidden-Output) layer neural network implemented on an FPGA. The network I wish to implement is a wide network with hidden neurons ~1000-2000. I want this to be implemented for highest data throughput with optimized resource utilization. Also want to software to be written for the implemented hardware. 5 Programování v C, Verilog / VHDL, Strojové učení, FPGA, Neural Networks Apr 17, 2018 Apr 17, 2018Ukončeno €120
CRYPTO MINING using VHDL in FPGA Details later.. I will check your BASIC.. And then recruit You 2 Verilog / VHDL, Těžební inženýrství, Digital Design, FPGA Apr 15, 2018 Apr 15, 2018Ukončeno €1705
Need a MC6803 replaced with FPGA Program a FPGA to work as a MC6803 on a device like a Digilent Cmod A7: Breadboardable Artix-7 FPGA Module. [url odstraněn, pro zobrazení se přihlaste] . will need relevant information to program multiple devices. 5 FPGA Apr 10, 2018 Apr 10, 2018Ukončeno €37
Serial Interface using Python Design a serial interface using Python for communication with FPGA. 5 Python, Verilog / VHDL, Uživatelské rozhraní / IA, Softwarová architektura, FPGA Apr 2, 2018 Apr 2, 2018Ukončeno €26
parallel multiply simulation -vhdl I need to create and minimize 2 small VHDL entities and their corresponding architectures. Can anyone help? I will provide with some files that are the basics to this, but still need to create 2 more. You need to be expert in VHDL language and have knowledge of computer architecture. 13 Programování v C, Inženýrství, Verilog / VHDL, Microcontroller, FPGA Mar 29, 2018 Mar 29, 2018Ukončeno €27
Electronic Systems - Mode B - Expert I am looking for someone who is familiar with and have access to the following Electronic systems/subjects: - Op-Amps - Multisim - FPGA/Quartus PRime - Mbed Microcontrollers - Digital Analogue converters (DAC) - using R-2R Ladder If you do not have relevant skills and access please do not apply Thank you 16 Elektronika, Microcontroller, PCB Layout, Circuit Design, FPGA Mar 29, 2018 Mar 29, 2018Ukončeno €498
JESD204B ADS54J20 vc707. - open to bidding I have a project where i need to receive ads54j20 data with interface jesd204b on vc707. if your are interested please let me know and we can discuss details in a chat. 6 Elektronika, Matlab a Mathematica, Verilog / VHDL, Microcontroller, FPGA Mar 28, 2018 Mar 28, 2018Ukončeno €590
Custom Arduino Pro Mini PCB layout Is it possible to make an custom made Arduino Pro Mini PCB? It needed to be made trough easyeda pcb and components from 1206 package Remove all holes traces that are x out. Remove reset button ? It needed to be programmable by and FTDI1232 programmer as regular arduino pro It also needed to added some other components to the board.I have a template that needed to be edited on easyeda, that y... 7 Microcontroller, PCB Layout, Arduino, Circuit Design, FPGA Mar 28, 2018 Mar 28, 2018Ukončeno €38
Absorption Chiller - open to bidding I have some work in MATLAB i need this work to be finished asap (1-2 days lower bids would be preferred i have more work like this so i want serious freelancers Time wasters are not allowed to bid here NOTE: Milestone will be after seeing the full work 4 Matlab a Mathematica, Verilog / VHDL, Algoritmy, Microcontroller, FPGA Mar 27, 2018 Mar 27, 2018Ukončeno €41
Embedded Systems use quartus compiler/simulator to design a [url odstraněn, pro zobrazení se přihlaste] displays left 16 bits of the result in hexadecimal format...................................................... 6 Programování v C, Verilog / VHDL, Microcontroller, C++ programování , FPGA Mar 26, 2018 Mar 26, 2018Ukončeno €26
Digital Alarm clock "verilog " I am looking for a freelancer to help me with my project. The skill required is Verilog. Project is to write verilog code for digital alarm clock an will be simulating in Modelsim and will need testbenches as well. message me for more details 13 Verilog / VHDL, Shromažďování, FPGA Mar 23, 2018 Mar 23, 2018Ukončeno €47
expert in simulink and vhdl needed I need an expert in simulink and vhdl 6 Inženýrství, Matlab a Mathematica, Verilog / VHDL, Elektrotechnika, FPGA Mar 23, 2018 Mar 23, 2018Ukončeno €18
FPGA NIST5 Cryptocurrency miner I am looking for a person who will make FPGA NIST5 Cryptocurrency miner. I need full unrolled NIST5 core. NIST5: blake512 -> groest512 -> jh512 -> keccak512 -> skein512 Perfect performance: 1x (Example: FPGA at 400MHz clock generates 400Mega Hash / secound) Language: VHDL FPGA: Xilinx 7 series 6 Verilog / VHDL, FPGA Mar 23, 2018 Mar 23, 2018Ukončeno €606
Design a Video codec H.264 Processor for Face recognition using Artificial intelligence algorith. Hi This is my research project. i want to design a video codec h.264 processor for face recognition. i this project i wrote verilog hdl coding and completed Ai algorithm for face recognition. so the next steps is to do the cross compilation of h.264 verilog coding with AI Algorithm. so iam expecting that to complete cross compilisation of h.264 verilog code with Ai algorith... 2 Programování v C, Inženýrství, Matlab a Mathematica, Verilog / VHDL, FPGA Mar 23, 2018 Mar 23, 2018Ukončeno €88
Verilog / VHDL, Microcontroller, Elektrotechnika, FPGA Mar 18, 2018 Mar 18, 2018Ukončeno
Academic writing I need someone who is expert in academic writing and EE engineering communication and radar field and also embedded systems FPGA, the page's number will be around 50, and the topic and results and design are ready just need to be written. 42 Technické psaní, Elektrotechnika, Výzkumná práce, FPGA Mar 15, 2018 Mar 15, 2018Ukončeno €103
test_audi in vivado sdk this is my problem : " 'XPAR_AXI_GPIO_0_BASEADDR' undeclared (first use in this function)" 2 FPGA Mar 14, 2018 Mar 14, 2018Ukončeno €22
stepper motor controller A stepper motor controller in verilog , 15 Elektronika, Verilog / VHDL, Microcontroller, Elektrotechnika, FPGA Mar 11, 2018 Mar 11, 2018Ukončeno €156
vhdl expert needed2 Expert in VHDL is needed to do a project 9 Inženýrství, Elektronika, Verilog / VHDL, Elektrotechnika, FPGA Mar 3, 2018 Mar 3, 2018Ukončeno €20
FPGA-eMMC interface Design and develop a interface logic for reading and writing to and from eMMC device to support 300Mbps data rate to Video encoder. - timelines - 2-3 weeks. 3 Programování v C, Elektronika, Verilog / VHDL, Microcontroller, FPGA Mar 1, 2018 Mar 1, 2018Ukončeno €298
vhdl or verilog project autoamate a door handle using vhdl or verilog 26 Inženýrství, Verilog / VHDL, Microcontroller, Elektrotechnika, FPGA Feb 27, 2018 Feb 27, 2018Ukončeno €87
Add serial connection to verilog project I have some existing code but need to add a serial connection to the hardware. More details to be provided. 15 Programování v C, Verilog / VHDL, Microcontroller, Softwarová architektura, FPGA Feb 27, 2018 Feb 27, 2018Ukončeno €52
Implement RSA algorithm synthesized code (512 bit) in Verilog Hi, I would like to implement RSA algorithm synthesized code in Verilog up to 512 bit of encryption. - Encryption data output size can vary from 16-bit to 512 bits. - Prime number generation: two random prime number generated through LFSR and should be stored in FIFO - For every iteration different public and private key pairs should be produced. Kindly cont... 9 Inženýrství, Verilog / VHDL, FPGA Feb 24, 2018 DnesUkončeno €87
DDR3 memory controller interface using nexys video for read write multiple images We are working on nexys video board and we are trying to access DDR3 memory using IPCORE in vivado design suite software. We want to read and write data into DDR3 memory using nexys video board. 6 Programování v C, Verilog / VHDL, Microcontroller, Vestavěný software, FPGA Feb 21, 2018 Feb 21, 2018Ukončeno €138
Verilog Servo controller I'm looking for someone who can write me a verilog HDL code for a servo controller 7 Programování v C, Verilog / VHDL, Microcontroller, Elektrotechnika, FPGA Feb 18, 2018 Feb 18, 2018Ukončeno €23
An expert in FPGA is required I would like someone to help me build a simple FPGA Kernel for a certain gaming system. 4 Programování v C, Verilog / VHDL, Microcontroller, Elektrotechnika, FPGA Feb 12, 2018 Feb 12, 2018Ukončeno €122
FPGA QAR Project I have a QAR file that I cannot compile into a POF or PLD file, I would like someone with experience in FPGA to do it. It must be someone with real good knowledge of FPGA. 14 Elektronika, Verilog / VHDL, Microcontroller, Elektrotechnika, FPGA Feb 12, 2018 Feb 12, 2018Ukončeno €403
FPGA CONSOLE I would like someone to help me build a simple FPGA Kernel for a certain gaming system. 5 Programování v C, Elektronika, Verilog / VHDL, Microcontroller, FPGA Feb 11, 2018 Feb 11, 2018Ukončeno €17
Use edaplayground to run a carry lookahead adder need a 4-bit carry look ahead adder to be coded in system Verilog using edaplayground. 1) write system Verilog model for CLA 2) parameterize for N bits 3) generate/write test bench that works 11 Programování v C, Verilog / VHDL, Microcontroller, Softwarová architektura, FPGA Feb 8, 2018 Feb 8, 2018Ukončeno €20
FIR Filter Reference Design in Verilog We are looking for a FIR filter design in Verilog with the following requirements: - 16-bit input, 16-bit fixed coefficient - 39-bit output - 256 taps Please provide 2 implementations: 1. serial implementation using 1 multiplier 2. partial parallel implementation with 4 multiplers 5 Verilog / VHDL, FPGA Feb 4, 2018 Feb 4, 2018Ukončeno €180
Petalinux on ZC706 I am looking for someone who has done work on Petalinux on ZC706 or Zedboard. The person MUST have done projects of Ethernet, PS Ram usage, external permanent memory storage using PCIe based drive, SPI control. I need to develop a project using above features. 1 Verilog / VHDL, FPGA Jan 29, 2018 Jan 29, 2018Ukončeno €136
Project for Constantin R. Hi Constantin R., I noticed your profile and would like to offer you my project. We can discuss any details over chat. 3 Microcontroller, PCB Layout, , Arduino, Circuit Design, FPGA Jan 12, 2018 Jan 12, 2018Ukončeno €5018
SFP communication with FPGA Coding required for FPGA to SFP communication 13 Elektronika, Verilog / VHDL, Microcontroller, Elektrotechnika, FPGA Jan 6, 2018 Jan 6, 2018Ukončeno €734
VHDL for programming FPGA board Hi, I run a small sales business in the video game industry. I am looking for someone with VHDL experience to assign pins on an FPGA board for an old video game system, to a new pre-designed break out board to allow the system to use HDMI. Please contact for details. 18 Verilog / VHDL, FPGA Jan 2, 2018 Jan 2, 2018Ukončeno €104
Convert some VHDL to Verilog Contact me for more details. All I need done is porting some VHDL to Verilog. 18 Inženýrství, Verilog / VHDL, Microcontroller, Softwarová architektura, FPGA Dec 23, 2017 Dec 23, 2017Ukončeno €97
Need an expert in ASIC board Hello, everyone! I need you to design ASIC board for mining BTC. If you are an expert in this field, please bid this project. We can discuss more details over chat. Thanks in advance. 4 Elektronika, Výroba, Microcontroller, Elektrotechnika, FPGA Dec 23, 2017 Dec 23, 2017Ukončeno €3228
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