Verilog / VHDL Jobs

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Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Zaměstnat Verilog / VHDL Designers

18 zakázek nalezeno, ceny v EUR

RISC Pipelined Processor Verilog 6 dní left

Attached I have my simulation of a 32-bit RISC pipelined processor (picture also attached), and I have a few errors in the code that won't let it compile. I am trying to find someone to simply aide in the debugging process so I can continue my work, I am hoping it would be done in the next day or two.

Elektrotechnika Elektronika FPGA Microcontroller Verilog / VHDL

€28 (Avg Bid)

€28 Průměr. nabídka

3 nabídky

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RISC Pipelined Processor in Verilog 6 dní left

I implemented the system that is attached in the picture, but when it came time to compile it I ran into a few errors. I want someone to help troubleshoot said errors, and then help create an assembly language program to MUL two 32-bit numbers to make a 64-bit answer within the Verilog environment to prove out the initial system. Shouldn't be complicated I'm just stuck.

Shromažďování Microcontroller Verilog / VHDL x86/x64 Assembler

€72 (Avg Bid)

€72 Průměr. nabídka

3 nabídky

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Design a neural network 6 dní left

Design a neural network in MATLAB/Simulink to configure the coefficients of the PID controller. The control object is a complex system with variable parameters. Programming skills are welcome

Elektrotechnika Elektronika Inženýrství Matlab a Mathematica Verilog / VHDL

€409 (Avg Bid)

€409 Průměr. nabídka

11 nabídky

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Precision PWM generation (1hz...40khz +/- 0.1Hz) 5 dní left

Hi, You will have to generate Precision PWM of 0...40khz +/- 0.1Hz. Refer the attachment and I have tried with STM32 using HRTIM but there is 0.34hz deviation at 30002 Hz. So it doesnt meet the requirement. I request pl have a look and you need to provide the right solution and design here to achieve this.

Elektrotechnika Elektronika Inženýrství Microcontroller Verilog / VHDL

€49 (Avg Bid)

€49 Průměr. nabídka

9 nabídky

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Microblaze programming 5 dní left

Looking for someone with good knowledge of microblaze and vhdl

Programování v C FPGA Java Matlab a Mathematica Verilog / VHDL

€118 (Avg Bid)

€118 Průměr. nabídka

9 nabídky

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Help Build Verilog Program 5 dní left

Need someone that is deeply knowledgeable in verilog programming. Need to be ABLE to build the CPU, build memory-less, combinational components and sequential components (i.e create mux and adder's in ALU), implement 2 stage pipeline for RISC-V Processor, etc.

Programování v C Elektronika FPGA Microcontroller Verilog / VHDL

€36 (Avg Bid)

€36 Průměr. nabídka

9 nabídky

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ADC VHDL for spartan 3a 5 dní left

I want to make the interface between the sinewave function generator and FPGA kit via ADC that belong to the same kit 1. Show the result on the test - bench window 2.I Want to show the practical result on LCD screen 3. Also use the leds to show the digital value for analog value

FPGA Verilog / VHDL

€126 (Avg Bid)

€126 Průměr. nabídka

8 nabídky

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need help with a seven segment on Nexys 4 DDR Development board 5 dní left

need help with a seven segment on Nexys 4 DDR Development board

FPGA FPGA Coding Verilog / VHDL

€68 (Avg Bid)

€68 Průměr. nabídka

3 nabídky

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CPLD converter, dual I2S codecs to TDM 4 dní left

The project's goal is to have two I2S codecs, both at the same samplerate, selectable 48/96/192KHz, connected to a CPLD and the CPLD to provide a TDM protocol for connection to a MCU. Codecs will have 48/96/192KHz, stereo, 32bits sample depth and will work at I2S protocol. Codecs will perform both capture and playback concurrently. The TDM protocol should have 4 slots for channels. Some po...

Elektrotechnika Elektronika FPGA Microcontroller Verilog / VHDL

€210 (Avg Bid)

€210 Průměr. nabídka

4 nabídky

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FPGA based clock debouncer cum digital filter 4 dní left

Hi, This project has a digital input and digital output. You need to design and program a FPGA for filtering the digital input and give to digital output. Get Input signal --> debounce logic --> send to output Input range (0Hz .. 1MHz) --> Output 0Hz --> 350KHz 1) when the input is on for more than 2ns , turn on the output 2) if input is off for 5ns, turn off the output 3) Output mi...

Elektrotechnika Elektronika FPGA Microcontroller Verilog / VHDL

€47 (Avg Bid)

€47 Průměr. nabídka

11 nabídky

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System Verilog Alarm 4 dní left

Design Specifications for the Alarm Clock ▪ Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period is not wired up in the DE0-CV board) o Hours will be displayed in “military time” (meaning 00 through 23). o Whenever the ...

Elektrotechnika Elektronika FPGA Microcontroller Verilog / VHDL

€243 (Avg Bid)

€243 Průměr. nabídka

15 nabídky

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High Precision 0.1 accuracy Pt 100 4 ch input with I2C communication 4 dní left

we need Portable Pt 100 4 ch device , High Precision 0.1 accuracy with 2C communication , display with battery/5v power supply

Programování v C Elektrotechnika Elektronika Microcontroller Verilog / VHDL

€126 (Avg Bid)

€126 Průměr. nabídka

13 nabídky

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System verilog expert 3 dní left

more details will be given in the chat

Elektrotechnika Inženýrství FPGA Matlab a Mathematica Verilog / VHDL

€21 (Avg Bid)

€21 Průměr. nabídka

8 nabídky

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Verilog VHDL tasks 3 dní left

Searching for people who has good knowledge in digital logic, Verilog and VHDL

Elektrotechnika Inženýrství FPGA Microcontroller Verilog / VHDL

€15 (Avg Bid)

€15 Průměr. nabídka

13 nabídky

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VHDL Structural Model 3 dní left

I need to test a structural model of a sequence detector using t flip flops. I know my t equations, I have my entity and the testbench I am using to test the model. I need help constructing the structural model. It is based off a behavioral and dataflow model I already created. The software I'm using is Aldec.

Elektrotechnika Inženýrství Verilog / VHDL

€11 / hr (Avg Bid)

€11 / hr Průměr. nabídka

12 nabídky

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MIPS microprocessor design expert 3 dní left

more details will be given in the chat

Elektrotechnika Elektronika FPGA Microcontroller Verilog / VHDL

€170 (Avg Bid)

€170 Průměr. nabídka

3 nabídky

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VLSI circuit design and simulation using cadence 2 dní left

I need the project A done as per the document bellow A Transimpedence/Limiting Amplifier (TIA/LA). The TIA should take the input in form of current (0.7mA -5mA) , for a current value in range should give an out put Swing of about 10mV with a bandwidth of 6.5GHz The LA should take the input from TIA and give the output swing of 200-250 mV. Simulation software Cadence will be provided and will u...

Circuit Design Elektrotechnika Elektronika Inženýrství Verilog / VHDL

€123 (Avg Bid)

€123 Průměr. nabídka

10 nabídky

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Create a circuit to do parity detection on 4 bits using Xilinix ISE 1 den left

Create a circuit to do parity detection on 4 bits using Xilinix ISE, will provide complete details in the chat.

Verilog / VHDL

€36 (Avg Bid)

€36 Průměr. nabídka

10 nabídky

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