Verilog / VHDL Práce a soutěže

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers.
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Projekt/Soutěž Popis Nabídky/Návrhy Dovednosti Zahájeno Končí Cena EUR
Tcp sending on FPGA using verilog xgmii Tcp sending on FPGA using verilog xgmii xilinx vivado 2 Verilog / VHDL Apr 19, 2018 Dnes6d 19h €404
Sending and receiving tcpip xgmii packets over SFP+ This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server. 1 Verilog / VHDL, FPGA Apr 19, 2018 Dnes6d 18h €450
plc program and hmi design Simulation I have Program pLc program and Hmi design for academics project just to simulating the code with software need basic help 6 Inženýrství, Elektronika, Verilog / VHDL, Microcontroller, Elektrotechnika Apr 19, 2018 Dnes6d 15h €19
develop Simple SW to write on the IC Card/Server I have IC cards or integrated chip cards that i needed to write on them. So, i am looking for simple SW and support for successful testing of this beta version design. My design and solution is almost the same as access control however it has its own different use cases. So, let’s assume that I need to create SW solution for access control within a hotel or company using IC card i... 4 Programování v C, Elektronika, Verilog / VHDL, Microcontroller, PCB Layout Apr 19, 2018 Dnes6d 12h €230
translate C++ code in systemc. translate c++ code in systemc and implement constrained random verification methodology. 5 Programování v C, Verilog / VHDL, Softwarová architektura, C++ programování , Very-large-scale integration (VLSI) Apr 19, 2018 Dnes6d 11h €36
build a software translate c++ code in systemc. and implement constrained random varification methodology. 1 Verilog / VHDL, Softwarová architektura, C++ programování , Very-large-scale integration (VLSI) Apr 19, 2018 Dnes6d 11h €16
Create a DLX Data Path Using VHDL Looking for an experienced person that understands computer architecture and VHDL language to complete this task. The project will require you to create simulation files of each task that's asked in the attached document to verify it works properly. The code needs to be neat and commented in a way that explains what is happening in the code. 6 Verilog / VHDL, Microcontroller, Softwarová architektura, Shromažďování, FPGA Apr 18, 2018 Dnes6d 3h €152
build a software translate a C++ code in systemc module. 3 Programování v C, Verilog / VHDL, C++ programování Apr 18, 2018 Apr 18, 20185d 23h €25
convert the C++ language code in systemc. you have to translate C++ code in systemc language. 3 Programování v C, Verilog / VHDL, Softwarová architektura, C++ programování Apr 18, 2018 Apr 18, 20185d 21h €27
Do VHDL project on the ModelSim I want to do a VHDL project on ModelSim, all what you need will be in the attached document, i will need a report for the whole project ( explaining every file in the project and what it does ). I want phase 1 ( Design ) ASAP and the rest of the project within a week ( Maximum 10 days ). Please read the document carefully and if you have any questions contact me. Specify your price and time requir... 10 Inženýrství, Elektronika, Verilog / VHDL, Elektrotechnika, FPGA Apr 18, 2018 Apr 18, 20185d 15h €130
verilog expert only more details will be given in the chat 15 Inženýrství, Elektronika, Verilog / VHDL, Elektrotechnika, FPGA Apr 18, 2018 Apr 18, 20185d 13h €15
SoundLocator Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position 14 Java, Elektronika, Android, Verilog / VHDL, FPGA Apr 18, 2018 Apr 18, 20185d 12h €501
Serializer & Desrializer Implementation using ZC706 and MTX Serializer & Desrializer Implementation using ZC706 and MTX 6 Verilog / VHDL, FPGA Apr 17, 2018 Apr 17, 20185d 5h €23
OpenCL FPGA Code modification I am looking for someone to modify the OpenCL code base of an AMD focused Crypto Mining Software and optimize it for OpenCL Based FPGA using this package [url odstraněn, pro zobrazení se přihlaste] Please respond directly with any questions such as specific mining software and such. 8 Programování v C, Verilog / VHDL, Kryptografie, OpenCL, FPGA Apr 17, 2018 Apr 17, 20185d €1873
Circuit at logism implement a digital circuit in Logisim for a door lock. 3 Elektronika, Verilog / VHDL, Microcontroller, Elektrotechnika, Circuit Design Apr 17, 2018 Apr 17, 20184d 20h €20
expert in vivado vhdl needed expert in vivado and vhdl needed asap 8 Inženýrství, Verilog / VHDL, Microcontroller, Elektrotechnika, FPGA Apr 17, 2018 Apr 17, 20184d 17h €20
digital logic design circuit in logisim there should be A and B inputs and the circuit should check if the A is divisible by B or not. and division should be worked like 10-2=8-2=6-2=4-2=2-2=0 then 10(a)is divisible by 2(b). we have only 30 minutes to do. 7 Inženýrství, Elektronika, Verilog / VHDL, Elektrotechnika, Circuit Design Apr 17, 2018 Apr 17, 20184d 15h €104
digital circuit in logisim we should draw a circuit in logisim. there should be 2 input like A and B. the circuit should check if A is dibisible by B or not. you should work with ALU. and division should be worked like 10-2=8-2=6-2=4-2=2-2=0 then 10(a)is divisible by 2(b) 4 Elektronika, Verilog / VHDL, Microcontroller, Elektrotechnika, Circuit Design Apr 17, 2018 Apr 17, 20184d 15h €17
Signal Peak Detector, Digital Design - Command Processor I am currently working on peak detector using VHDL entry (Modelsim and Xilinx), to design logic design in FPGAs to fulfill my free time. There are two parts, which are command processor and data processor. However, I have completed the data processor part, so only command processor left and I have no idea how to complete it. I plan to accomplish this task by next Sunday, 22nd April before I starte... 7 Inženýrství, Elektronika, Matlab a Mathematica, Verilog / VHDL, Elektrotechnika Apr 17, 2018 Apr 17, 20184d 15h €37
Circuit in Logism Given two 4-bit integers, A and B, build a circuit that can outputs 1 if A is divisible by B, or 0 otherwise. It should be done using 4 bit ALU 8 Inženýrství, Elektronika, Verilog / VHDL, Elektrotechnika, Circuit Design Apr 17, 2018 Apr 17, 20184d 13h €53
Logisim Digital Logic Design using four bit ALU, given two numbers A and B we need to find if A is divisible by B 14 Inženýrství, Elektronika, Verilog / VHDL, Elektrotechnika, FPGA Apr 17, 2018 Apr 17, 20184d 12h €66
Neural Network on an FPGA I want to get a simple 3 layer (Input-Hidden-Output) layer neural network implemented on an FPGA. The network I wish to implement is a wide network with hidden neurons ~1000-2000. I want this to be implemented for highest data throughput with optimized resource utilization. Also want to software to be written for the implemented hardware. 4 Programování v C, Verilog / VHDL, Strojové učení, FPGA, Neural Networks Apr 17, 2018 Apr 17, 20184d 7h €141
VHDL digital lock I have a project that im working on and need to do it by 4/27/2018. I need to show the simulation that the program is running and may need help understanding how it runs. I want someone to do the project and explain to me how it was done and to show me that the program is running (simulation). I have attached a file of the description and the board I will be using, it has and integrated ADC chip ... 17 Verilog / VHDL, Microcontroller, Digital Design, FPGA Apr 15, 2018 Apr 15, 20183d 2h €119
CRYPTO MINING using VHDL in FPGA Details later.. I will check your BASIC.. And then recruit You 3 Verilog / VHDL, Těžební inženýrství, Digital Design, FPGA Apr 15, 2018 Apr 15, 20182d 19h €1800
programming mplab programm an fm receiver chip to be able a radio to work mp lab software using c or c++ everything exxplained in files that will be sent 18 Programování v C, Verilog / VHDL, Microcontroller, C++ programování , Arduino Apr 13, 2018 Apr 13, 201814h 45m €175
Experts on Communication system, Digital Signal Processing, and Matlab needed 2 - 12/04/2018 18:48 EDT Like mentioned above, I have many task on this. I need experts in this field who can help. I do not want someone who cannot work at a reduced rate since order is regular. Only people who is experienced in this field should bid. Thanks 6 Inženýrství, Matlab a Mathematica, Verilog / VHDL, Elektrotechnika, Telekomunikační inženýrství Apr 12, 2018 Apr 12, 20181h 51m €25
Experts on Communication system, Digital Signal Processing, and Matlab needed Like mentioned above, I have many task on this. I need experts in this field who can help. I do not want someone who cannot work at a reduced rate since order is regular. Only people who is experienced in this field should bid. Thanks 3 Inženýrství, Matlab a Mathematica, Verilog / VHDL, Elektrotechnika, Telekomunikační inženýrství Apr 12, 2018 Apr 12, 20181h 42m €16
Mips, Verilog project Small project on computer architecture 20 Verilog / VHDL Apr 9, 2018 Apr 9, 2018Ukončeno €17
State Machine and Timing Diagram for Embedded System State Machine and Timing Diagram for Embedded System. More details to be provided. 17 Verilog / VHDL, Vestavěný software Apr 9, 2018 Apr 9, 2018Ukončeno €36
OS work ( Printing Service) In this work, I need a coder who will design a programming solution to a variant of the boundedbuffer producer/multi-consumer problem using semaphores. The main goal of the task is to get familiar with the basic concepts of InterProcess Communication (IPC) and threads. Your implementation will be based on the following: shared memory, locks, semaphores and threads. More details will be prov... 8 Programování v C, Java, Verilog / VHDL, C++ programování , Programování Apr 8, 2018 Apr 8, 2018Ukončeno €26
Systemverilog TCPIP model Looking for a SystermVerilog TCPIP model which drives the MAC data to TCPIP DUT and analyze the data from DUT. Need some customization depending on the RTL. 3 Verilog / VHDL Apr 6, 2018 Apr 6, 2018Ukončeno €150
NS3 simulation using c++ and ubunto NS3 simulator NS3 simulation using c++ and ubunto NS3 simulator 5 Programování v C, Linux, Verilog / VHDL, Softwarová architektura, C++ programování Apr 6, 2018 Apr 6, 2018Ukončeno €294
ns3 project c++ ubunto needed i need this simulation for ns3 using c++ 4 Programování v C, Linux, Verilog / VHDL, Softwarová architektura, C++ programování Apr 6, 2018 Apr 6, 2018Ukončeno €190
Simple SCADA WEB page Web Page for monitoring data of sensor Login Security Historical reports Mobile COmpatibility Good Desing If you are interested you should write me a message saying you have experience in labview 9 PHP, Inženýrství, Verilog / VHDL, Softwarová architektura, LabVIEW Apr 6, 2018 Apr 6, 2018Ukončeno €146
Vhdl coding for a small project 1. Do some for loop in vhdl 2. Do some multiplication in vhdl 3. Add registers at input and output 4 Verilog / VHDL Apr 4, 2018 Apr 4, 2018Ukončeno €26
Serial Interface using Python Design a serial interface using Python for communication with FPGA. 5 Python, Verilog / VHDL, Uživatelské rozhraní / IA, Softwarová architektura, FPGA Apr 2, 2018 Apr 2, 2018Ukončeno €26
Project for Usama S. Hi Usama S., I noticed your profile and would like to offer you my project. We can discuss any details over chat. 7 Elektronika, Verilog / VHDL, Výzkumná práce, LabVIEW, , Akademické psaní Apr 2, 2018 Apr 2, 2018Ukončeno €28
FPGA Programming Crypto Miner I am looking for someone that can program or port an existing Windows or Linux mining program for AMD GPU's to a Xilinx Kintex-7 FPGA I will provide details and Github privately 9 Programování v C, Elektronika, Verilog / VHDL, Microcontroller, Elektrotechnika Mar 30, 2018 Mar 30, 2018Ukončeno €1154
parallel multiply simulation -vhdl I need to create and minimize 2 small VHDL entities and their corresponding architectures. Can anyone help? I will provide with some files that are the basics to this, but still need to create 2 more. You need to be expert in VHDL language and have knowledge of computer architecture. 13 Programování v C, Inženýrství, Verilog / VHDL, Microcontroller, FPGA Mar 29, 2018 Mar 29, 2018Ukončeno €27
Implementation of Leach protocol on tinyos I have a Wireless sensor network project, I need to implement the leach protocol on a hardware that is compatible with tinyos. You must have: -Theorical background on WSN. -Experience on implementation on Tinyos. 1 Programování v C, Bezdrátové, Inženýrství, Verilog / VHDL, C++ programování Mar 29, 2018 Mar 29, 2018Ukončeno €15
JESD204B ADS54J20 vc707. - open to bidding I have a project where i need to receive ads54j20 data with interface jesd204b on vc707. if your are interested please let me know and we can discuss details in a chat. 6 Elektronika, Matlab a Mathematica, Verilog / VHDL, Microcontroller, FPGA Mar 28, 2018 Mar 28, 2018Ukončeno €584
Build me iv.file I have a project that deal with LABView app, or as it called iv. file. I need someone who is good at creating scheme and using LABView 7 Verilog / VHDL, Microcontroller, Softwarová architektura, LabVIEW, Arduino Mar 28, 2018 Mar 28, 2018Ukončeno €24
Implementation of Leach protocol on tinyos I have a Wireless sensor network project, I need to implement the leach protocol on a hardware that is compatible with tinyos. You must have: -Theorical background on WSN. -Experience on implementation on Tinyos. 3 Programování v C, Bezdrátové, Inženýrství, Verilog / VHDL, C++ programování Mar 28, 2018 Mar 28, 2018Ukončeno €49
Absorption Chiller - open to bidding I have some work in MATLAB i need this work to be finished asap (1-2 days lower bids would be preferred i have more work like this so i want serious freelancers Time wasters are not allowed to bid here NOTE: Milestone will be after seeing the full work 4 Matlab a Mathematica, Verilog / VHDL, Algoritmy, Microcontroller, FPGA Mar 27, 2018 Mar 27, 2018Ukončeno €41
RFID Read and Write using VHDL or Arduino A code that will read data from RFID tag 1 using a RC522 Rfid reader and verify that to a stored value. Upon successful authentication, it will read data from RFID Tag 2. Then the program will generate a random number and store it in RFID tag 1 and also update the previous system stored value of tag 1. 12 Verilog / VHDL, Arduino Mar 27, 2018 Mar 27, 2018Ukončeno €20
Embedded Systems use quartus compiler/simulator to design a [url odstraněn, pro zobrazení se přihlaste] displays left 16 bits of the result in hexadecimal format...................................................... 6 Programování v C, Verilog / VHDL, Microcontroller, C++ programování , FPGA Mar 26, 2018 Mar 26, 2018Ukončeno €26
Digital Alarm clock "verilog " I am looking for a freelancer to help me with my project. The skill required is Verilog. Project is to write verilog code for digital alarm clock an will be simulating in Modelsim and will need testbenches as well. message me for more details 13 Verilog / VHDL, Shromažďování, FPGA Mar 23, 2018 Mar 23, 2018Ukončeno €46
expert in simulink and vhdl needed I need an expert in simulink and vhdl 6 Inženýrství, Matlab a Mathematica, Verilog / VHDL, Elektrotechnika, FPGA Mar 23, 2018 Mar 23, 2018Ukončeno €17
FPGA NIST5 Cryptocurrency miner I am looking for a person who will make FPGA NIST5 Cryptocurrency miner. I need full unrolled NIST5 core. NIST5: blake512 -> groest512 -> jh512 -> keccak512 -> skein512 Perfect performance: 1x (Example: FPGA at 400MHz clock generates 400Mega Hash / secound) Language: VHDL FPGA: Xilinx 7 series 6 Verilog / VHDL, FPGA Mar 23, 2018 Mar 23, 2018Ukončeno €599
Design a Video codec H.264 Processor for Face recognition using Artificial intelligence algorith. Hi This is my research project. i want to design a video codec h.264 processor for face recognition. i this project i wrote verilog hdl coding and completed Ai algorithm for face recognition. so the next steps is to do the cross compilation of h.264 verilog coding with AI Algorithm. so iam expecting that to complete cross compilisation of h.264 verilog code with Ai algorith... 2 Programování v C, Inženýrství, Matlab a Mathematica, Verilog / VHDL, FPGA Mar 23, 2018 Mar 23, 2018Ukončeno €87
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