Verilog / VHDL Práce a soutěže
Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers.
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| Projekt/Soutěž | Popis | Nabídky/Návrhy | Dovednosti | Zahájeno | Končí | Cena EUR | |
|---|---|---|---|---|---|---|---|
| Dual axis sun tracking system using myRIO | I need someone who could develop the program on labview using myrio to track sun and move the panels accordingly. I am using servo motors. | 8 | Verilog / VHDL, Microcontroller, Elektrotechnika, Vestavěný software, LabVIEW | Oct 22, 2017 | Dnes6d 16h | €127 | |
| Digital system and microprocessor small task -- 2 | small task on digital system and microprocessor using verilog amount usd 20 time 1 day | 8 | Elektronika, Verilog / VHDL, Microcontroller, Elektrotechnika, FPGA | Oct 22, 2017 | Dnes6d 8h | €27 | |
| Electrical engineering expert needed to do vhdl code | Electrical engineering expert needed to do vhdl code $30 pay | 9 | Inženýrství, Elektronika, Verilog / VHDL, Elektrotechnika, Akademické psaní | Oct 22, 2017 | Dnes6d 8h | €46 | |
| Digital system and microprocessor small task | small task on digital system and microprocessor using verilog amount usd 20 time 1 day | 9 | Elektronika, Verilog / VHDL, Microcontroller, Elektrotechnika, FPGA | Oct 21, 2017 | Oct 21, 20175d 22h | €20 | |
| Custom Verilog design | We need to build a custom Verilog design. Please message for further details. | 12 | Inženýrství, Verilog / VHDL, Elektrotechnika, LabVIEW, FPGA | Oct 21, 2017 | Oct 21, 20175d 18h | €20 | |
| project verilog | Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat. | 10 | Programování v C, Inženýrství, Verilog / VHDL, Elektrotechnika, FPGA | Oct 21, 2017 | Oct 21, 20175d 8h | €10 | |
| VLSI design and testability using SPICE/ Verilog/VHDL | An applied project may involve using tools such as Spice, Verilog/VHDL, etc. to demonstrate its success | 9 | Verilog / VHDL, Very-large-scale integration (VLSI) | Oct 20, 2017 | Oct 20, 20174d 23h | €377 | |
| Logisim Software Tasks | Hi I need someone who is good with Logisim Software to complete some tasks. | 9 | Inženýrství, Elektronika, Verilog / VHDL, Elektrotechnika | Oct 20, 2017 | Oct 20, 20174d 18h | €22 | |
| Power Generation Simulation using LabVIEW | Power Generation Simulation using LabVIEW. Power generation stations will often consist of a number of individual generators where each generates a proportion of the overall station’s output. Need two separate applications. Application 1 and Application 2. | 8 | Matlab a Mathematica, Verilog / VHDL, Elektrotechnika, LabVIEW, Arduino | Oct 20, 2017 | Oct 20, 20174d 9h | €46 | |
| Digital design using Verilog | Use Basys 3 Board and Vivado 2016.2 I'll share the rest details | 7 | Verilog / VHDL, Microcontroller, Elektrotechnika, LabVIEW, FPGA | Oct 20, 2017 | Oct 20, 20174d 9h | €36 | |
| VHDL Radio Clock + python script | Need help in VHDL everything is mentioned on the PDF | 7 | Elektronika, Verilog / VHDL, Testování softwaru, Elektrotechnika, FPGA | Oct 19, 2017 | Oct 19, 20173d 12h | €61 | |
| Project for Gabriel G. | I need help with capsim practice rounds | 4 | Projektový Management, Telemarketing, Excel, Matlab a Mathematica, Verilog / VHDL | Oct 18, 2017 | Oct 18, 20173d 1h | €21 | |
| verilog project | making verilog on quartus II (cyclone IV) | 11 | Inženýrství, Verilog / VHDL, Softwarová architektura, Shromažďování, FPGA | Oct 18, 2017 | Oct 18, 20172d 19h | €123 | |
| Cloudsim project | I want someone to work on programming part in cloudsim that includes migration, Placement, scheduling and power consumption. | 2 | Programování v C, Java, Verilog / VHDL, Softwarová architektura, C++ programování | Oct 18, 2017 | Oct 18, 20172d 8h | €52 | |
| Verilog programming - 18/10/2017 00:34 EDT | Simple verilog programming project. Create an ALU with full [url odstraněn, pro zobrazení se přihlaste] is desired is a Verilog system that can operate as a calculator with a set of logic gates attached. Other details provided later. | 14 | Verilog / VHDL | Oct 18, 2017 | Oct 18, 20172d 7h | €85 | |
| Verification Of Motion Estimator Using UVM | Verification Of Motion Estimator Using UVM(Universal Verification Methodology) | 5 | Verilog / VHDL, Elektrotechnika, Very-large-scale integration (VLSI) | Oct 17, 2017 | Oct 17, 20172d 6h | €202 | |
| Verilog programming | Simple verilog programming project. Create an ALU with full [url odstraněn, pro zobrazení se přihlaste] is desired is a Verilog system that can operate as a calculator with a set of logic gates attached. Other details provided later. | 5 | Verilog / VHDL | Oct 17, 2017 | Oct 17, 20172d 3h | €76 | |
| ASIC Design in Verilog | This project is related to Computational Neural Networks | 2 | Matlab a Mathematica, Verilog / VHDL, Neural Networks | Oct 17, 2017 | Oct 17, 20171d 23h | €130 | |
| VHDL Radio clock | everything is going to be explained on the pdf | 11 | Elektronika, Verilog / VHDL, Microcontroller, Elektrotechnika, FPGA | Oct 17, 2017 | Oct 17, 20171d 22h | €34 | |
| Design of audio visualiser using DE2-115 Altera board | I want to implement an audio visualizer on the screen of the voice spoken through the mic or played using SD card. | 4 | Verilog / VHDL | Oct 17, 2017 | Oct 17, 20171d 19h | €199 | |
| Matlab power system Simulation using Simulink -- 2 - 17/10/2017 07:15 EDT | My project is about the microgrid protection. I need to simulate a simple power network system (Figure 6 in the attachment) using Simulink, For the inverter I need to make some controller that can control when the microgrid is in grid mode or islanded mode (Figure 3-5 in the attachment). It is best if I can get the result same or similar with the one that in the journa | 14 | Inženýrství, Elektronika, Matlab a Mathematica, Verilog / VHDL, Elektrotechnika | Oct 17, 2017 | Oct 17, 20171d 14h | €116 | |
| Matlab power system Simulation using Simulink | My project is about the microgrid protection. I need to simulate a simple power network system (Figure 6 in the attachment) using Simulink, For the inverter I need to make some controller that can control when the microgrid is in grid mode or islanded mode (Figure 3-5 in the attachment). It is best if I can get the result same or similar with the one that in the journa | 10 | Inženýrství, Elektronika, Matlab a Mathematica, Verilog / VHDL, Elektrotechnika | Oct 17, 2017 | Oct 17, 20171d 12h | €133 | |
| Elektronika, Verilog / VHDL, Microcontroller, Elektrotechnika, LabVIEW | Oct 16, 2017 | Oct 16, 20171d 6h | |||||
| netlist construction in EE using C++ | refactor the sample code by using the c++ | 9 | Programování v C, Verilog / VHDL, C# Programování, Elektrotechnika, C++ programování | Oct 16, 2017 | Oct 16, 201719h 26m | €115 | |
| verilog project | want verilog code on fpga i want soon | 2 | Inženýrství, Verilog / VHDL, Softwarová architektura, LabVIEW, FPGA | Oct 16, 2017 | Oct 16, 201718h 3m | €7 | |
| ASIC Designs and Development | Hello. I am into a project that involves creating PCB / ASIC design with FPGA/CLPD. The specified ASIC Architecture as a product needs to be able calculate one or more algorithms connected through some type of data socket. Performance and power is important. I am interrested to get in touch with a board designer and vhdl developer that have knowledge both with electrical layouts and vhdl. ... | 7 | Inženýrství, Elektronika, Verilog / VHDL, Elektrotechnika, PCB Layout | Oct 16, 2017 | Oct 16, 201711h 54m | €15 | |
| veriloghdl code for calculation area | THis must implement on quartus( altera FPGA cyclone IV) | 4 | Programování v C, Verilog / VHDL, Microcontroller, C++ programování , FPGA | Oct 16, 2017 | Oct 16, 201711h 5m | €88 | |
| making verlog hdl code | calculataion area in black and white image on fpga ( cyclone IV) | 8 | Programování v C, Verilog / VHDL, Microcontroller, Elektrotechnika, C++ programování | Oct 16, 2017 | Oct 16, 20177h 40m | €106 | |
| VHDL Coursework | help in VHDL codes ,, everything will be explained later | 14 | Inženýrství, Elektronika, Verilog / VHDL, Elektrotechnika | Oct 15, 2017 | Oct 15, 2017Ukončeno | €48 | |
| fpga software | I want to read programmes in FPGA chips | 17 | Programování v C, Verilog / VHDL, Softwarová architektura, FPGA | Oct 15, 2017 | Oct 15, 2017Ukončeno | €351 | |
| creation of hardware module using verilog which will be able to communicate with the memory of the processor | using Verilog which will be able to communicate with the memory of the processor | 4 | Verilog / VHDL | Oct 14, 2017 | Oct 14, 2017Ukončeno | €53 | |
| simple verilog hdl code | calculate each area in black and white image | 11 | Programování v C, Inženýrství, Verilog / VHDL, Microcontroller, FPGA | Oct 13, 2017 | Oct 13, 2017Ukončeno | €40 | |
| Simple Verilog Project | Design a perception timer that measures the time for a user to respond to a request to complete a simple task. I'll send the rest details for part 3. | 8 | Inženýrství, Matlab a Mathematica, Verilog / VHDL, Elektrotechnika, FPGA | Oct 13, 2017 | Oct 13, 2017Ukončeno | €20 | |
| Color space conversions and FPGA's | 3 pages report in two parts on: (i) fundamental information about FPGAs and their programming, and (ii) standard color spaces and formulas for converting those color spaces into other ones. (Plagarism free) finished in 3 days maximum. | 9 | Inženýrství, Verilog / VHDL, Elektrotechnika, FPGA | Oct 13, 2017 | Oct 13, 2017Ukončeno | €56 | |
| Build software | Looking for expert in FPGA and verilog | 18 | Programování v C, Verilog / VHDL, Softwarová architektura, C++ programování , FPGA | Oct 12, 2017 | Oct 12, 2017Ukončeno | €408 | |
| Statcom in simulink Power electronics expert -- 2 | Statcom in simulink Power electronics expert needed | 9 | Elektronika, Matlab a Mathematica, Verilog / VHDL, Elektrotechnika, FPGA | Oct 11, 2017 | Oct 11, 2017Ukončeno | €140 | |
| Want to develop robotic program and test the same with simulation to check feasibility of and automation idea | Existing : Manual labours are lifting filled 25 kg bags from stack of machine palletised load (40 bags per wooden pallet, and loading into trucks, containers. Automation solution : Using three axis gantry robot, vacuum lifting end tool and smart programming to create fully automatic truck loading system. All above only on simulation, 3d models to check feasibility of solutions and then to us... | 5 | Matlab a Mathematica, Verilog / VHDL, Softwarová architektura, Vývoj softwaru, Programování | Oct 11, 2017 | Oct 11, 2017Ukončeno | €3978 | |
| VLSI PROJECTS | FIND THE ATTACHED IEEE [url odstraněn, pro zobrazení se přihlaste] REQUIREMENTS | 4 | Verilog / VHDL, FPGA, Very-large-scale integration (VLSI) | Oct 11, 2017 | Oct 11, 2017Ukončeno | €73 | |
| Statcom in simulink Power electronics expert | Statcom in simulink Power electronics expert needed | 9 | Elektronika, Matlab a Mathematica, Verilog / VHDL, FPGA | Oct 11, 2017 | Oct 11, 2017Ukončeno | €97 | |
| Convert a code from Aptech Gauss language into Matlab with Parallel processing. | I have a code written in Aptech Gauss program that I want to convert into Matlab and I want the code to run under CUDA power in Matlab. | 3 | Matlab a Mathematica, Verilog / VHDL, Softwarová architektura, CUDA, Vývoj softwaru | Oct 10, 2017 | Oct 10, 2017Ukončeno | €130 | |
| Prelab | Write VHDL code | 7 | Verilog / VHDL | Oct 10, 2017 | Oct 10, 2017Ukončeno | €23 | |
| dimensionality reduction using PCA | we will consider use of PCA for simple dimensionality reduction, i.e., determining the signal subspace when there are more observations than the underlying latent variables—signals. The main assumption here is that both the noise and signals are independent and identically distributed Gaussians, however the the signals are correlated among themselves while the noise components are not, ... | 14 | Matlab a Mathematica, Verilog / VHDL, Analýza konečných prvků (Finite Element), CUDA, FPGA | Oct 10, 2017 | Oct 10, 2017Ukončeno | €347 | |
| Altera DE115 - Audio signal processing | Record voice , Add and Remove Noise and play back recording. Design and implement the verilog code on an Altera DE2-115 Development Board. Available Hardware Microphones, Speakers | 9 | Verilog / VHDL, Microcontroller, Vestavěný software, Shromažďování, FPGA | Oct 10, 2017 | Oct 10, 2017Ukončeno | €192 | |
| Audio Signal Processing | AIM - Record Audio , Add and Remove Noise and play back audio. To design and implement the Embedded System centred on an Altera DE2-115 Development Board. The project should be based on a Verilog HDL implementation. Available Hardware In addition to the DE2-115 board, the following hardware devices are available. If you wish to do a project requiring hardware support but don’t see the... | 7 | Verilog / VHDL, Microcontroller, Elektrotechnika, Vestavěný software, FPGA | Oct 10, 2017 | Oct 10, 2017Ukončeno | €432 | |
| Sequence Diagram | There is a service class called PurchaseOrder that is called when a customer makes a purchase. It has a public method purchase(Account, Order). It does the following. a. Call [url odstraněn, pro zobrazení se přihlaste]() b. Call [url odstraněn, pro zobrazení se přihlaste](Account) c. Call [url odstraněn, pro zobrazení se přihlaste]() d. [url odstraněn, pro zobrazení... | 6 | Verilog / VHDL, Softwarová architektura, PLC a SCADA, Analýza konečných prvků (Finite Element), Technické kreslení | Oct 10, 2017 | Oct 10, 2017Ukončeno | €31 | |
| Matlab Program for Harmonics Analysis for a sampled data (Data in excel format) | Need a Matlab program to perform Harmonics Analysis for a sampled data (data in Excel format). Matlab Codes must structured to read data from Excel file. Please find the attached Excel file [url odstraněn, pro zobrazení se přihlaste] | 22 | Excel, Matlab a Mathematica, Verilog / VHDL, Softwarová architektura, Vývoj softwaru | Oct 7, 2017 | Oct 7, 2017Ukončeno | €18 | |
| UML/MARTE modeling | I want to build an interface(which consists of rules) to transform any MML model to a UML-MARTE model using AGG(algebraic graph transformation). | 1 | Verilog / VHDL, UML Design, Analýza konečných prvků (Finite Element), SAS, CATIA | Oct 7, 2017 | Oct 7, 2017Ukončeno | €499 | |
| matlab report making 10 pages minimum | hi discussion via chat no front milestone need it in 12 hrs 10 mages maximum paper should be in IEEE formats no plagiarism is there.. please give a good quote | 10 | Matlab a Mathematica, Verilog / VHDL, LaTeX, Matematika, Fyzika | Oct 7, 2017 | Oct 7, 2017Ukončeno | €41 | |
| Matlab Write a Function for Forward Kinematics of the RPR Robot | Input Format are the joint angles in radian, as shown in the figure is the extension of the prismatic joint in inches, as shown in the figure Output Format R is a 3x3 rotation matrix representing (Note: where represents a point in frame x) pos is a 4x3 matrix where each row contains the x,y,z coordinates represented as [x y z] in matrix form. Each row is the x,y,z coordinates of a point... | 16 | Matlab a Mathematica, Verilog / VHDL, Softwarová architektura, Analýza konečných prvků (Finite Element), Vývoj softwaru | Oct 7, 2017 | Oct 7, 2017Ukončeno | €32 | |
| String compare algorithm | need an algorithm that would compare two long strings delimited by | | 3 | Matlab a Mathematica, Verilog / VHDL, Algoritmy, CUDA, Strojové učení | Oct 7, 2017 | Oct 7, 2017Ukončeno | €1666 |
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