SMC Interface and SPI Slave Logic for CPLD Project

A proposal has not yet been provided

Dear Sir/Madam, I, on behalf of Dyumnin Technologies am submitting this proposal in response to your project for SMC Interface and SPI Slave Logic for CPLD Project. Dyumnin Technologies was founded in 2016 by a Semiconductor Industry professional with over 15 years of experience in Digital IP design in the field of wired and wireless communication and display technology with Industry leaders like Texas Instruments and Intel. I have summarized my understanding of the requirements and deliverables below, You can contact me over chat and we can discuss/schedule a discussion to exchange the details of the requirements. i.e. : * Identifying the application specific SPI commands that need to be implemented. * Specification for Requirement #1 and #5 * My understanding is, Requirement #6 is a general feature of the FPGA and does not need any design action. Tentatively I propose the following schedule. Inputs: ====== 1> Clarification on the SPI command set. 2> Specification for the Highspeed and GPIO features. Deliverables: ========== 1> Delivery of SPI/QSPI interface in a week. (Req #2,#3,#4) 2> Delivery of the HS I/F and GPIO in a week(Req #1,#5) Once we have a clarity on the specification. We can finalize the project schedule and intermediate milestones, and you can award the bid based on the schedule and deliverable agreement.

I have very good experience in SPI implementation in CPLDs which will let me finish your project on time