Design the emitter follower amplifier shown in Figure 1 to provide a midband gain of 0.8, lower cutoff
frequency of 100 Hz, and an upper cutoff frequency of 5 MHz. Verify and compare the theoretical
answer with the results produced by simulation using PSPICE A/D.
also finding Rsig , c1,c2, RL
hi i am an electrical engineer. i have vast experience related to circuit design and analog electronics. i have done emitter follower designs. i have can do this circuit for you. let me know if you are interested. we can discuss further on chat.
Expertise in electronic and LTSPICE as I have completed various projects related to it. I can provide you your complete task in decided time frame with quality work.
We can discuss further details in the message box
Regards
Hello,
Extremely interested in your emitter follower amplifier designing!
I have background in electrical engineering and multi-discipline task management. Specialties include electric system and process controls design, electrical equipment, PCB, and development of a System Reliability Improvement Program.
I can assure you that our work is strictly in accordance with current international quality control procedures and we adopt a set of scientific and strict working flow.
Look forward to speak to you soon.
We are a team for engineering experienced in electronics circuit designing and simulations.
We have designed analog and digital circuit on pSpice formour clients and sent them report as per their
requirement.
We have a good knowledge about the BJT circuit and we can analysis the circuit as well on pSpice.
Queries:
1. What are the deliverables?
2. timeline of the project?
3. Milestones of the project?
Looking forward to work with you and for further discussion.