Hi guys, I've done a simple design to test the SRAM of Digilent Cmod A7 FPGA board.
This is how it works: Using a terminal through UART, I send the input data and address to the SRAM. Then I send address where to read, and I get back the data previously written.
Everything works OK except the controller.
I need someone to review my design and fix it.
6 freelanceů na tento projekt zveřejnilo nabídku v průměrné hodnotě $19
Hello, I have overall 10 years of experience in FPGA Design and Verification. I am interested in this project. Please provide your design will have a look and fix it. Thanks Kartik