PLL Frequency Measure and adjust microcomputer compensated crystal oscillator (MCXO) STM32 and Si5351A

FPGA Expert here I carefully read your project requirements and I understand that you want to design PLL Frequency Measure and adjust microcomputer compensated crystal oscillator FPGA based project. Yes I will design it for you because I have well experience to work on FPGA based projects. Come on chat for more discussions. Thanks waqas

HI, I think I undestand your project and I like the idea of using an FPGA. However, I'm not sure if the internal plls of an fpga can be used to measure clk phase and freq. One method could be using an fpga and 2 freerunning counters, clocked one with each clock. Every, lets say 1 second, the counters value are reset to 0, and the 2 values are compared, (the ref clk can be used to measure the time). If the counter triggered with the measured source is greater, then it means the frequency is higher and needs to be lowered, if its lower the opposite. This method is precise but it could trigger some oscilations with the controller if its not tuned properly, and the maximum accuracy would be limited to 2 clock cycles per second (with a syncronous design on an fpga you can measure only discrete clocks missaligments, not the phase between them). So with a 1 second sample period you can measure (2/25e6)s = 80 ns discrepancy which means a relative difference in frequency of (25e6+2)/(25e6) or 8e-6 percent. Idk your accuracy requirements, and this is an ideal case, the implemented version can be less acurate. I have experience with fpga designs, mostly using xilinx devices and altera (before intel). The logic to implement inside the fpga looks simple but since there are two clock sources its not trivial to manage it. Thanks, Juan Cruz. (Im in argentina, idk if the time difference is a problem)