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VLSI Design Engineer - Part Time - 20/09/2018 08:19 EDT

Front End VLSI Design engineer Part Time in Bangalore

Looking for expert FPGA Design engineer with RTL Design [Verilog]

Proven track record of designing, developing, prototyping, and testing high speed FPGA designs

Experience in Verilog programming & experience with Xilinx devices and development tools

Design Simulation experience [Modelsim]

Candidate should be familiar with solving IEEE research papers, algorithms, architectures using VerilogHDL.

Dovednosti: Elektronika, FPGA, Verilog / VHDL

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O zaměstnavateli:
( 0 recenzí ) Bengaluru, India

Identifikační číslo projektu: #17806358

4 freelanceů na tento projekt zveřejnilo nabídku v průměrné hodnotě ₹10833

rubelsarkar161

Hi... If you need Analog/Digital layout design engineer in future please contact...

₹11111 INR za 3 dní
(1 recenze)
2.0
₹11111 INR za 30 dní
(2 Recenzí)
2.6
kartikprmr

Hello, I have expertise in ASIC/FPGA Design & Verification and worked on following languages. VHDL Verilog Systemverilog/UVM MATLAB Python Perl I am willing to work in this project as part time job. Please get back Další

₹10000 INR za 7 dní
(0 Recenzí)
0.0
₹11111 INR za 5 dní
(0 Recenzí)
0.0