Probíhá

Design a Floating Point (FP) arithmetic unit in VHDL

Design a Floating Point (FP) arithmetic unit, using IEEE 794 single precision binary numbers, which implements the following operations:

• Addition

• Subtraction

• Multiplication

• Comparison

The FPU should be based on a Kogge-Stone adder (KSA) [1], a parallel prefix form carry look-ahead adder.

Dovednosti: Inženýrství, Verilog / VHDL

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O zaměstnavateli:
( 3 recenzí ) Beirut, Lebanon

Identifikační číslo projektu: #13744686

Uděleno uživateli:

ahmedmohamed85

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$222 USD za 3 dní
(276 recenzí)
7.5

6 freelanceů na tento projekt zveřejnilo nabídku v průměrné hodnotě $229

raulbehl

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$250 USD za 5 dní
(45 Recenzí)
5.5
ducdctoandh

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$250 USD za 3 dní
(50 Recenzí)
5.5
OlektraGroup

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$205 USD za 3 dní
(6 Recenzí)
3.0
iffi37

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$222 USD za 8 dní
(0 Recenzí)
0.0
nikj1101

A proposal has not yet been provided

$222 USD za 15 dní
(0 Recenzí)
0.0