Verification IP development for AXI Protocol using system Verilog
₹1500-12500 INR
K zaplacení v momentě doručení
VIP component development for AXI3.0 protocol with support for various features like burst type, burst size, protection, out of order, overlapping, aligned,WRAP,fixed burst . Develop BFM, Generator, Monitor, and Coverage models and also the slave model.
Identifikační číslo projektu: #15529477
O projektu
3 Freelnceři na tento projekt zveřejňují nabídky v průměru ₹11296
I would be able to finish this proficiently as I have know this protocol well and my current project also involves this project. Relevant Skills and Experience I am working as a Sr. ASIC Verification Engineer in one o Další