I am a third-year student from the Department of Electronics and Electrical Communication Engineering at the Indian Institute of Technology, Kharagpur. This is the domain of my interest. I have more than 6 months of continuous experience in verilog. I am in great touch now. You can test me.
I shall be committed to my work. I shall readily acquaint myself with any pre-requisites needed for the project. I hope to be able to go beyond the problem statement and produce the quality of the research work required for the project. I request you to please consider.
Thank you.
Hey, I'm working in industry as RTL design engineer. I've worked on various projects involving verilog and system verilog programming language. I'm sure I can help you in your project.
Share more details about your project.