VHDL/Verilog expert with Virtex-5 board needed

Hello freelancers! The goal of this project is to help us investigate hardware-efficient implementation of the Espresso stream cipher and to compare it to Grain-128 and Trivium in terms of area, delay, latency and power energy consumption so we can decide which suits us the best. Your tasks will include: • Investigating hardware optimization techniques targeting Xilinx FPGA Devices • Evaluating its speed, throughput, area, power consumption, and energy efficiency and comparing the results to Grain-128 and Trivium. I am looking for a candidate expert on VHDL/Verilog and with a Virtex-5 board to work on ISE 14.7. We will use ModelSim and Xilinx ISE tools in this project. The deliverables will be: a. code b. testbenches c. measurements Notes: 1- Espresso stream cipher is already implemented 2- It is required to compare espresso stream cipher with Grain-128 and Trivium, so is Grain-128 and Trivium are already implemented and evaluated its speed, throughout ...etc, or I have to evaluate for the three algorithms and make a comparison? answer Algorithms exist but are not implemented to run on FPGA (this is true for espresso as well). All will be need to be done on it (test bench, simulation, synthesis, etc.) to make the comparison The deadline is in 25 January and budget aprox $120-150 AUD. I would be happy to talk for more info in case you are interested :) Thank you a lot for your time and i will be happy to help!