CAN bus controller.

od VerilogFPGA
CAN bus controller.
CAN bus controller.
CAN bus controller.

ARINC825_controller module configures and manages the process of work chip SJA1000. SJA1000 chip is a controller CAN-bus network . Controller SJA1000 has two modes: Reset mode and Operation mode. At power-up or hardware reset of the SJA1000 controller goes into Reset mode and the module ARINC825_controller performs initial configuration and setup. Operation mode there is an exchange of messages on the CAN bus. Transmission and reception of messages by the controller SJA1000 is done automatically in accordance with the CAN Protocol. During message transmission module ARINC825_controller receives a message via interface Avalon MM Slave, puts it in a Transmit Buffer of the SJA1000 controller and sets the Transmit Request flag in the command register. The received message is placed in the Receive Buffer, then set the Receive Interrupt flag. The sending / receiving message is transmitted on the Avalon MM Master interface to memory.

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FPGA, Matlab, Verilog, System Verilog, Altera, Xilinx, Quartus II, ModelSim, Nios, Microblaze, C / C++ Experience with: - Video processing, reception and transmission video on LVDS. Have own library: frame buffer, test pattern generator, mixer, switch, sync generator, mjpeg - Embedded CPUs Nios II and MicroBlaze - High-speed interfaces such as FiberChannel, Ethernet, HDMI, Avrora - All slow-rate interfaces - DDR, NandFlash, CFI-Flash - SDH - DVI-transceivers and CameraLink To DisplayPort Converter NCS8801

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