Gauss filter in VHDL
€30-250 EUR
K zaplacení v momentě doručení
Έχω μια εργασία στην οποία πρέπει να φτιάξω σε κώδικα VHDL ένα φίλτρο Gauss, και το οποίο θα έχει είσοδο μια εικόνα και στην έξοδο θα δίνει την εικόνα φιλτραρισμένη. Μετά τον κώδικα πρέπει να τον τρέξω σε modelsim και τα pixel της εξόδου θα πρέπει να τα δω στην κυματομορφη εξόδου.
Identifikační číslo projektu: #30332076
O projektu
Uděleno uživateli:
6 Freelnceři na tento projekt zveřejňují nabídky v průměru €210
Dear sir, I am a digital design engineer expert in FPGA and ASIC design flows using Verilog and VHDL programming. Also, I am experienced with Vivado, ISE, Vivado IPs, SDK, Quartus, Design Compiler, IC Compiler and othe Další
Hello, I've complete MS Electric Engineering (Control System). I have plenty of experience in firmware development and micro-controller developments. My Core Skills are: -MATLAB, SIMULINK MODLING AND SIMULATION - STM Další
Hi! I have understood your requirnment, about your project with every detail of it. I am an Electrical Engineer with more then 9 years experience in electronics, circuit design, Verilog, PCB layout, microcontrollers, Další
Dear Client! I'm wonderful for your project. I'm an Electrcical Engineer and have been working for 4 years in this field. I'm good in logic digital circuit and have good skill in verilog/vhdl.
Dear client I'm interested in your project, and I can do it with the perfect method and time. I'm an expert in designing and developing analog and digital integrated circuits using Cadence virtuoso, Quartus; Modelsim; Další
