ModelSim, Verilog

$10-30 USD

Probíhající

Zveřejněno

před více než 4 roky

$10-30 USD

Zaplaceno při doručení

This should include the Verilog HDL code of your MPZ design and simulation results to show the correct behavior, or any other interesting observation (e.g. maximum clock frequency of the design).

Verilog / VHDL

FPGA

Electrical Engineering

Software Testing

IČ projektu: 21396225

O projektu

2 nabídky

Vzdálený projekt

Aktivní před 5 roky

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2 freelanceři nabízejí v průměru $20 USD za tuto práci

@Worker404

Hi there! I am an electronics engineer with lots of experience in Verilog/VHDL. I have worked on projects like UART, FIFO Ram, Encoders etc. on Spartan 3E kit. I have seen the attached problem and the paper and I will be able to provide you a professional quality work for a good rating and review. About my freelancing, the best part is that I keep constant contact with my employer and provide revisions for free. Looking forward to working with you.

$20 USD v 2 dnech

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@JiangZhengHe

Hello! To dear client Thanks for sharing your project. I am a signal processing expert. I have wonderful 8+years experiences in signal processing. I correctly know about various items such as FFT & FIR & IIR filter that are widely used in signal processing field and wireless communication field . I also have experience in very complex radar signal processing. So, not only I can do signal processing using Quartue II, Xilinx IDE and Xilinx vivado, but can do all of things related signal processing and VHDL(Verilog HDL) language. That's why I can satisfy your need fully. Let's discuss more with chatting. Best Regards

$20 USD v 1 dni