FPGA Edge Detection Algorithm Comparison

₹600-1500 INR

Probíhající

Zveřejněno

před 22 dny

₹600-1500 INR

Zaplaceno při doručení

I'm in need of an FPGA expert with experience in VIVADO, to implement different edge detection algorithms, including Canny and Sobel, for the purpose of comparing their performance. Key Requirements: - Implement edge detection algorithms in VIVADO: The primary task is to develop and deploy edge detection algorithms in an FPGA, with a focus on Canny and Sobel techniques. - Algorithm Performance Evaluation: The main goal of this project is to compare the efficacy and efficiency of different edge detection algorithms, so you should have a strong background in image processing and be able to provide a thorough analysis of their performance. - Knowledge of other edge detection algorithms: While Canny and Sobel are the main focus, knowledge of other edge detection algorithms such as Laplacian would be advantageous. Ideal Skills and Experience: - Proficiency in FPGA programming and development using VIVADO. - Strong background in image processing and algorithm development. - Prior experience in implementing edge detection algorithms. - Experience in algorithm comparison and evaluation would be a plus. The ideal candidate should have excellent communication skills and be able to provide regular updates on the progress of the project. The final deliverable should include a detailed performance analysis of the implemented algorithms. CODE FOR CANNY IS ALREADY DONE JUST NEED TO INTEGRATE OTHER ALGORITHMS

Verilog / VHDL

Matlab and Mathematica

Electrical Engineering

FPGA

Engineering

IČ projektu: 38030471

O projektu

2 nabídky

Vzdálený projekt

Aktivní před 21 dny

Chcete si vydělat nějaké peníze?

E-mailová adresa

Výhody podávání nabídek na Freelancer

Stanovte si rozpočet a časový rámec

Získejte za svou práci zaplaceno

Načrtněte svůj návrh

Registrace a podávání nabídek je zdarma

Uděleno:

@ahmedosama8272

Hello Sir, I hope you're doing well today. I want to express my interest in this task, I'm eager to learn whatever it takes to complete a job and have all the experience mentioned in the description. Throughout my experience in digital IC design, I'm excellent with using Verilog, SystemVerilog, and VHDL, and newly to Chisel-based Scala HDL, I worked on many projects like microprocessors, Crypto cores, DSP Cores, Memory Design, and bus design. Also, I worked with many FPGA projects including Zedboard ultra-scale, PYNQ-Z2, DE0, DE1 SoCs, and Basys-3, with design and power optimization techniques using Xilinx VIVADO and Intel Quartus prime. Finally, I worked with many digital IC verification projects using SystemVerilog - UVM. You can take a look at my previous projects on my GitHub repos =================================> [login to view URL] I look forward to discussing more about this task and also looking forward to sharing my knowledge with you. Sincelery, Ahmed Osama.

₹1 000 INR v 5 dnech

0,0

(0 recenze)

0,0

2 freelanceři nabízejí v průměru ₹10 500 INR za tuto práci

@Netrapug

I am an FPGA expert with more than 8 years of experience in designing various digital systems using VHDL/Verilog. I will be able to implement various edge detection algorithms using Vivado. I have previous experience on edge detection algorithms and its implementation. Lets start the project as soon as possible after discussing thorough requirements through messages.

₹20 000 INR v 7 dnech